An MTJ memory device comprises three basic layers, a free ferromagnetic layer, an insulating tunneling barrier, and a pinned ferromagnetic layer. The magnetization moments of the free ferromagnetic layer are free to rotate under an external magnetic field. The pinned ferromagnetic layer can comprise a ferromagnetic layer and/or an anti-ferromagnetic layer that pins the magnetic moments in the ferromagnetic layer. Thus, the magnetization moment of the pinned ferromagnetic layer is pinned in a fixed direction. A very thin insulation layer forms the tunneling barrier between the pinned and free ferromagnetic layers.
The MTJ memory device can be electrically represented as a resistor. The size of the resistance depends upon the orientation of the magnetization of the free ferromagnetic layer and the pinned ferromagnetic layer. As is understood by those skilled in the art, the MTJ memory device has a relatively high resistance when the magnetic vectors are misaligned (point in opposite directions) and a relatively low resistance when the magnetic vectors are aligned. That is, an MTJ memory device stores a bit of information as the relative orientation of the magnetizations of the free ferromagnetic layer and the pinned ferromagnetic layer. In other words, the magnetization of each MTJ memory device at any given time assumes one of two stable orientations. These two stable orientations, referred to as “parallel” and “anti-parallel” magnetic orientation, represent logic values of “0” and “1”, for example.
To write or change the state in the MTJ memory device, an external magnetic field can be applied that is sufficient to completely switch the stable orientation of the magnetization of the free ferromagnetic layer. To sense states in the MTJ memory device, a read current can be applied through the MTJ memory device. As the magneto-resistance varies according to the state stored in the MTJ memory device, the logic state of the MTJ memory device can be sensed by obtaining the voltage difference across the MTJ memory device. An MRAM array comprises a plurality of MTJ memory devices, and the binary logic data of entire MRAM array is typically read by applying a sensing current flowing perpendicularly through selected MTJ memory device. Switches are implemented in conventional methods to block the stray read current path. In addition, the switches are also used to avoid write disturbance.
Switching devices such transistors and/or diodes are often employed to block current leakage or “sneak” current often occurring in the MRAM circuitry, usually during the read operation for the MTJ devices. The switching devices are employed to block sneak current paths in the MRAM array that might otherwise be present. In addition, such switches are also used to avoid write disturbance during writing operations. For example, some “non-disturbing” programming circuit designs employ two transistors for each MTJ device or memory “cell” or “bit.” However, such designs provide insufficient cell density due to the relatively large area occupied by the switching device in relation to the MTJ cell. Another approach employs one transistor or diode for each bit to control the read current and block the sneak current paths, although such designs also do not offer sufficiently MRAM density for today's market demands.
In U.S. Pat. No. 6,606,263, Tang discloses a non-disturbing programming scheme for an MRAM array. FIG. 1 shows the structure of the 2T1R MRAM cell 100 disclosed in Tang. To write data to memory element 14A, switches 10A and 10B are selected, and the magnetic field generated by write current IW through program line 15A switches the direction of the magnetic moments of the free ferromagnetic layer of memory element 14A. When switch 10C is selected, read current IT flows through bit line 12, memory element 14B, program line 15A, and switch 10C. Thus, data stored in memory element 14B is obtained by sensing the voltage level of bit line 12. While the cell structure in FIG. 1 effectively eliminates write disturbance, the cell density of the MRAM structure in FIG. 1 is poor.
In U.S. Pat. No. 5,640,343, Gallagher disclosed a magnetic memory array using magnetic tunnel junction devices in the memory cells. FIG. 2 shows the circuit 200 disclosed in Gallagher, which uses one switch for one bit to control the sense current and block all stray paths. A selected cell 20A is written by passing current IB through bit line 22A, and current IW through word line 24A. According to the “asteroid curve,” the magnetic field produced by either IB or IW alone in the region of the cells is less than the magnetic field required to change the magnetic state in a cell, thus, half-selected cells 20B (those over which only IB or IW alone is passing) are not written. The combination of magnetic fields from IB and IW is, however, sufficient to change the state of selected memory cell 20A.
In a read operation, a forward bias voltage is established across the selected cell 20A by pulling the word line 24 voltage down, and raising the bit line 22 voltage. In addition, unselected bit lines 24B and word lines 22B remain at standby voltages, thus, half-selected cells have a zero voltage drop from word line to bit line and do not conduct. The data stored in selected cell 20A is obtained by sensing the resistance thereof. The resistance of the selected cell determines the sense current that flows from the selected bit line to the selected word line through the selected memory cell.
U.S. Pat. No. 6,317,375 to Perner discloses a method and apparatus for reading memory cells of a resistive cross point array using a 2-step reading method with a specific voltage arrangement to block or reduce the sneak current. FIG. 3 depicts the cross point array 300 having a plurality of magnetic tunnel junction (MTJ) memory cells 31. The cross point array 300 includes n row lines 32 (also referred to as word lines) and m column lines 33 (also referred to as bit lines) that are perpendicular and pass over the row lines 32. An MTJ memory device 31 is located at an intersecting region of a row line 32 and a column line 33. The memory cell 31 is an MTJ device connected in series between a row line 32 and a column line 33.
FIGS. 4A and 4B are illustrations of sense and sneak path currents flowing through an electrical equivalent of a resistive cross point array (400A and 400B, respectively) of the device shown in FIG. 3. FIG. 4A shows an electrical equivalent of the memory cell array. A selected memory cell is represented by a first resistor 42A, and unselected memory cells are represented by second, third and fourth resistors 42B, 42C and 42D. The second resistor 42B represents the unselected memory cells along the selected bit line, the third resistor 42C represents the unselected memory cells along the selected word line, and the fourth resistor 42D represents the remaining unselected memory cells. If, for example, all of the memory cells 31 have a nominal resistance of about R and the array has n rows and m columns, then the second resistor 42B has a resistance of about R/(n−1), the third resistor 42C has a resistance of about R/(m−1), and the fourth resistor 42D has a resistance of about R/[(n−1)(m−1)].
The first resistor 42A maybe selected by applying the array voltage (Vs) to the crossing bit line and a ground potential to the crossing word line. Consequently, sense current (IS) flows through the first resistor 42A. However, the second, third and fourth resistors 42B, 42C and 42D are also coupled between the array voltage (Vs) and the ground potential. To mitigate the effects of sneak path currents during read operations, the same operating potential Vb=Vs is applied to the unselected bit line. If Vb=Vs, sneak path currents are blocked from flowing through the second and fourth resistors 42B and 42D, and a sneak path current S3 flowing through the third resistor 52C will be directed to the ground potential and, therefore, will not interfere with the sense current (IS).
Alternatively, the effects of the sneak path currents may be mitigated by applying the same operating potential Vb=Vs to the unselected word line, as shown in FIG. 4B. A sneak path current is blocked from flowing through the second resistor 42B. Sneak path currents S3 and S4 flowing through the third and fourth resistors 42C and 42D are not directed to the ground potential and, therefore, will not interfere with the sense current (IS). Thus, applying an equal potential to the unselected bit or word lines of the array can eliminate or reduce obscuration of the sense current (IS). Consequently, the sense current (IS) and, therefore, the resistance state of the selected memory cell are reliably determined. The circuitry disclosed in Perner provides a high MRAM cell density because no transistor is implemented for each bit. However, the reading method disclosed in Perner requires large power consumption and complicated circuitry because unselected word lines and bit lines are supplied additional bias during a reading procedure.
U.S. Pat. No. 6,421,271 to Gogl discloses an MRAM configuration 500, illustrated in FIG. 5, which comprises bit line 50 and word lines 51A and 51B crossing bit line 50 essentially perpendicularly, at a distance from one another. MTJ memory devices 51-54 are located between bit line 50 and word line 51A, and MTJ memory devices 55-58 are located between bit line 50 and word line 51B. The ends situated opposite bit line 50 of the memory cells 51-54 are connected with a drain or source of a switching transistor Tr1, while the ends situated opposite bit line 50 of memory cells 55-58 are connected to a drain or source of a switching transistor Ir2. A gate of transistor Tr1 is connected to word line 51A, and a gate of transistor Ir2 is connected to word line 51B. The source or drain of the switching transistors Tr1 and Ir2 are grounded.
During a read process, a predetermined voltage of 1V to 2V is applied to bit line 50. The transistors of all the word lines, except for the transistors of a particular word line, are thereby blocked. It is assumed here that in the example the transistors of word line WL1 conduct, i.e., in the example, transistor Tr1 is supposed to be turned ON. If now, for example, the MTJ memory device 52 is in a low-ohmic state (parallel magnetization of the two magnetic layers), while the remaining MTJ memory devices 51, 53 and 54 are in a high-ohmic state (anti-parallel magnetization of the magnetic layers), on word line 51A a corresponding signal is obtained that differs from the signal that is present on word line when all the TMR memory cells are in a high-ohmic state. In order to determine which of the memory cells 51-54 is in the low-ohmic state, a self-reference sensing scheme is implemented. This read method, however, is known as destructive-read, and a consequent procedure of data-restoration is required. Destructive rewriting of the original data to the read memory cell subsequent to the reading procedure consumes excess time and power.